Design and Implementation of High Speed and Low Power Carry Skip Adder
Marcy P M R
PG Scholar, VLSI Design, Sardar Raja College of Engineering, Alangulam, Tirunelveli, Tamil Nadu
M Vellapandia
Head Of The Department of ECE, Sardar Raja College of Engineering, Alangulam, Tirunelveli, Tamil Nadu
Receiving Date:
2016-07-02
Acceptance Date:
2016-08-16
Publication Date:
2016-09-17
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Abstract
The most timing critical part of logic design usually contains one or more arithmetic operations, in which addition is commonly involved. In VLSI applications, area, delay and power are the important factors which must be taken into account in the design of a fast adder. The Carry-skip adder reduces the time needed to propagate the carry by skipping over groups of consecutive adder stages, is known to be comparable in speed to the carry look-ahead technique while it use less logic area and less power. In this paper, a design of 8-bit Carry skip Adder by various existing logic styles are to be compared quantitatively and qualitatively by performing detailed using Xilinx v13.0.
Keywords:
Multipliers; logic design; VLSI applications
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