Deep Bhattacharjee
Electro-Gravitational Space Propulsion Laboratory (EGSPL), Bhubaneswar, Odisha, India
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http://doi.org/10.37648/ijrst.v16i02.004
This manuscript presents a claimed first-principles closure route for P versus NP, organized around a Fourier–geometric obstruction to polynomial-size circuit representation of satisfiability. The argument develops five interlocking layers: Fourier–Walsh analysis of Boolean functions, hypercontractive and random-restriction control of polynomial-size circuits, phase-transition cluster geometry for random satisfiability, a curvature-based saturation index on the Fourier cluster hypergraph, and a curvature-guided spectral descent that compresses low-complexity circuit profiles into negligible saturation regimes. The central comparison is between the high-level Fourier and cluster-saturation profile forced by SAT? and the exponentially small high-level profile available to polynomial-size circuit families. This comparison yields a level-wise Fourier discrepancy between SAT? and any polynomial-size circuit, giving SAT? ? P/poly and hence the claimed separation P ? NP. The revised manuscript tightens the closure by locking every transition to an explicit quantitative output: encoding normalization, Fourier mass transfer, circuit spectral compression, saturation-index comparison, descent monotonicity, and final non-uniform circuit lower bound. The final audit records the dependencies so that the claimed proof route is presented as a single exponent-tight chain from Boolean spectral obstruction to complexity-theoretic separation.
Keywords: P versus NP; Fourier entropy; spectral saturation; circuit lower bounds; curvatureguided descent.
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