An Optimized Shift Register Using Pulsed Latches
T Shobakar
PG Scholar, VLSI Design, Sardar Raja College of Engineering, Alangulam, Tirunelveli, Tamilnadu
S Muppudathi Sutha
Assistant Professor, Department of ECE, Sardar Raja College of Engineering, Alangulam, Tirunelveli, Tamilnadu
Receiving Date:
2016-06-23
Acceptance Date:
2016-08-10
Publication Date:
2016-09-12
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Abstract
Flip-flops (FFs) and latches are well known to be responsible for a large fraction of the power budget of microprocessors and VLSI systems. A new class of pulsed latches is introduced and experimentally assessed in 65-nm CMOS technology. Its conditional push–pull pulsed latch topology is based on a push-pull final stage driven by two split paths with a conditional pulse generator. A lowpower, high speed and area-efficient shift register using pulsed latches is designed in this project. A 256-bit shift register using pulsed latches was fabricated using a CMOS process with the power consumption is 1.2 mW at a 100 MHz clock frequency. Accordingly, the proposed class of pulsed latches goes beyond the current state of the art and is well suited for VLSI systems that require both high performance and energy efficiency. This is more than 1000 times faster than software processing running on a 3-GHz general-purpose processor.
Keywords:
Flip-flops (FFs); latches; Optimized Shift Register
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