Energy Efficient Multiplier With Adaptive Hold Logic
Y Sahaya Vincy
PG Scholar, VLSI Design, Sardar Raja College of Engineering, Alangulam,Tirunelveli, Tamil nadu
M Vellapandian
Assistant Professor,Department of ECE, Sardar Raja College of Engineering, Alangulam,Tirunelveli, Tamil nadu
Receiving Date:
2016-06-25
Acceptance Date:
2016-08-07
Publication Date:
2016-09-09
Download PDF
Abstract
Digital multipliers are among the most critical arithmetic functional units in many applications, such as the Fourier transform, discrete cosine transforms, and digital filtering. The throughput of these applications depends on multipliers, and if the multipliers are too slow, the performance of entire circuits will be reduced. Meanwhile, the negative bias temperature instability effect occurs when a pMOS transistor is under negative bias, increasing the threshold voltage of the pMOS transistor, and reducing multiplier speed. A similar phenomenon, positive bias temperature instability, occurs when an nMOS transistor is under positive bias. Both effects degrade transistor speed, and in the long term, the system may fail due to timing violations. Therefore, it is important to design reliable high-performance multipliers. In this paper, we propose an aging-aware multiplier design with novel adaptive hold logic (AHL) circuit. The multiplier is able to provide higher throughput through the variable latency and can adjust the AHL circuit to mitigate performance degradation that is due to the aging effect. Moreover, the proposed architecture can be applied to a column- or row-bypassing multiplier.
Keywords:
Energy Efficient Multiplier; Adaptive Hold Logic; pMOS transistor
References
- Y. Cao. (2013). Predictive Technology Model (PTM) and NBTI Model [Online]. Available: http://www.eas.asu.edu/∼ptm
- M. Olivieri, “Design of synchronous and asynchronous variable-latency pipelined multipliers,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 9, no. 4, pp. 365–376, Aug. 2001.
- B. C. Paul, K. Kang, H. Kufluoglu, M. A. Alam, and K. Roy, “Negative bias temperature instability: Estimation and design for improved reliability of nanoscale circuit,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 26, no. 4, pp. 743–751, Apr. 2007.
- B. C. Paul, K. Kang, H. Kufluoglu, M. A. Alam, and K. Roy, “Impact of NBTI on the temporal performance degradation of digital circuits,” IEEE Electron Device Lett., vol. 26, no. 8, pp. 560–562, Aug. 2005.
- R. Vattikonda, W. Wang, and Y. Cao, “Modeling and miimization of pMOS NBTI effect for robust naometer design,” in Proc. ACM/IEEE DAC, Jun. 2004, pp. 1047–1052
- Y.-S. Su, D.-C. Wang, S.-C. Chang, and M. Marek-Sadowska, “Performance” optimization using variable-latency design style,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 10, pp. 1874–1883, Oct. 2011.
- S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, “NBTI-aware synthesis of digital circuits,” in Proc. ACM/IEEE DAC, Jun. 2007, pp. 370–375.
- A. Calimera, E. Macii, and M. Poncino, “Design techniqures for NBTItolerant power-gating architecture,” IEEE Trans. Circuits Syst., Exp. Briefs, vol. 59, no. 4, pp. 249–253, Apr. 2012.
- K.-C. Wu and D. Marculescu, “Joint logic restructuring and pin reordering against NBTI-induced performance degradation,” in Proc. DATE, 2009, pp. 75–80.
- Y. Lee and T. Kim, “A fine-grained technique of NBTI-aware voltage scaling and body biasing for standard cell based designs,” in Proc. ASPDAC, 2011, pp. 603–608.
Back
