Ahamada Shreen J
M.E VLSI DESIGN, SCAD College of Engineering & Technology, Cheranmahadevi, Tamilnadu,
Prem Ananth R
Assistant Professor, SCAD College of Engineering & Technology, Cheranmahadevi, Tamilnadu
Download PDFWhile research in security and its implementation in hardware has been on-going for many decades, the concept of hardware security was not formally introduced until the emergence of hardware Trojans and their detection methods. For most of existing Trojan detection methods, scalability becomes a concern. Therefore, researchers started to look into post-deployment methods leveraging post-deployment side-channel fingerprinting and on-chip equivalence checking. The key idea here was that stealthy hardware Trojans may easily evade detection methods during testing stage but, if triggered, they will cause large impact to side-channel fingerprinting or to circuit functionality. To increase HT detection sensitivity, this paper introduces the low-level HTH protection scheme by filling the unused resources of the FPGA with low-level counterfeit logic (LLCL).The proposed scheme identifies unused resources within the FPGA device and propose counterfeit logic cells for different resources of FPGAs. The proposed scheme significantly reduces the chance of application space HTH attacks by giving no free configurable resource for HTHs insertion in the design’s bit stream. The malicious inclusion can either disturb the functionality of the original design, incur device fluctuations such as warming up or transistor aging.The proposed system can detect HTs, even if the HT size is small. Simulation results show that the proposed method achieves up to 100% HT detection rate
Keywords: limestone; cement production; SWIR; band ratio; Landsat 8; network analysis
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